<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Stefan,<div><br></div><div>Intel Nehalem changes it's clock frequency in 133MHz increments as a way to do power management. I believe you can even halt the CPU and resume it without messing things up too badly in their architecture. I also don't think that's a new idea, but I forget who did it first.</div><div><br></div><div>Dave<br><div><div>On Jan 7, 2010, at 2:20 AM, Stefan M. Petters wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">
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Hi,<br>
<br>
both correct. However, you can usually access the BIOS at boot time.
The CPU core frequency is not going to change (unless you do DFS, clock
gating, etc).<br>
Only thing left on PC style architecture is that the BIOS might decide
to scale down regardless, if it deems the CPU is getting too hot.<br>
<br>
Stefan.<br>
<br>
Frank Kaiser wrote:
<blockquote cite="mid:026691588FEC5D48AE1A8857256F656A0644E3@os-s03.open-synergy.com" type="cite">
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<div class="Section1"><p class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: rgb(0, 32, 96);" lang="EN-US">XScale is not a x86/IA32 architecture.<o:p></o:p></span></p><p class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: rgb(0, 32, 96);" lang="EN-US">On a system running OKL4 you cannot access any BIOS
functions, because
they are all real mode implementations while OKL4 is running in
protected mode.<o:p></o:p></span></p><p class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: rgb(0, 32, 96);" lang="EN-US"><o:p> </o:p></span></p><p class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: rgb(0, 32, 96);" lang="EN-US">Frank<o:p></o:p></span></p>
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<div style="border-style: solid none none; border-color: rgb(181, 196, 223) -moz-use-text-color -moz-use-text-color; border-width: 1pt medium medium; padding: 3pt 0cm 0cm;"><p class="MsoNormal"><b><span style="font-size: 10pt; font-family: "Tahoma","sans-serif"; color: windowtext;">From:</span></b><span style="font-size: 10pt; font-family: "Tahoma","sans-serif"; color: windowtext;">
<a class="moz-txt-link-abbreviated" href="mailto:developer-bounces@okl4.org">developer-bounces@okl4.org</a>
[<a class="moz-txt-link-freetext" href="mailto:developer-bounces@okl4.org">mailto:developer-bounces@okl4.org</a>] <b>On Behalf Of </b>Stefan M.
Petters<br>
<b>Sent:</b> Thursday, January 07, 2010 10:58 AM<br>
<b>To:</b> Frank Kaiser<br>
<b>Cc:</b> Peter Nguyen; developer<br>
<b>Subject:</b> Re: [okl4-developer] PMCs<o:p></o:p></span></p>
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</div><p class="MsoNormal"><o:p> </o:p></p><p class="MsoNormal">Hi,<br>
<br>
Frank Kaiser wrote: <o:p></o:p></p><p class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: rgb(0, 32, 96);">Hello</span><o:p></o:p></p><p class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: rgb(0, 32, 96);"> </span><o:p></o:p></p><p class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: rgb(0, 32, 96);" lang="EN-US">Most of modern x86 processors provide the TSC for
performance
monitoring. According to what I remember from INTEL’s x86 architecture
documentation it is guaranteed that the TSC will not overflow within 10
years.
This is far beyond a system’s uninterrupted operating time, therefore I
see no
reason for an overflow interrupt etc.</span><o:p></o:p></p><p class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: rgb(0, 32, 96);" lang="EN-US">The common approach is to read and store the TSC at a
tracepoint
and calculate time differences between associated tracepoints. The main
difficulty is to determine the absolute timebase, because this is
highly
dependent on the specific CPU and chipset in use, and on the system’s
clocking.</span><o:p></o:p></p><p class="MsoNormal">TSCs count CPU core clock cycles. So it becomes
somewhat
iffy when you start frequency scaling. On some XScale processors you
have the
option of saving power by gating the core clock. IIRC that means also
the TSC
will be halted.<br>
Unless you do the energy saving thing, it becomes pretty trivial to
find out
the core CPU frequency.<br>
Under Linux <br>
cat /proc/cpuinfo<br>
will tell you and BIOS usually also does.<br>
On Windows you can look up the System info.<br>
<br>
Regards,<br>
Stefan.<o:p></o:p></p>
<div><p class="MsoNormal">-- <o:p></o:p></p>
<div><p class="MsoNormal"><span class="stress1"><span style="font-size: 9pt; font-family: "Verdana","sans-serif";">Stefan M.
Petters</span></span><span style="font-size: 9pt; font-family: "Verdana","sans-serif";"><br>
</span><span class="nostress1"><span style="font-size: 9pt; font-family: "Verdana","sans-serif";">CISTER
Research Unit</span></span><span style="font-size: 9pt; font-family: "Verdana","sans-serif";"><br>
<span class="parstyle1"> </span><br>
</span><span class="highlight1"><span style="font-size: 9pt; font-family: "Verdana","sans-serif";">ISEP
- IPP</span></span><span class="parstyle1"><span style="font-size: 9pt;">
| Rua
Dr. António Bernardino de Almeida 431</span></span><span style="font-size: 9pt; font-family: "Verdana","sans-serif";"><br>
<span class="parstyle1">4200-072 Porto | Portugal </span><br>
<span class="parstyle1">T +351 22 83 40 529 | <a moz-do-not-send="true" href="http://www.cister.isep.ipp.pt/people/stefan+m%2E+petters">Homepage</a>
</span></span><o:p></o:p></p>
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<div> <span class="parstyle"> <span class="stress">Stefan M. Petters</span><br>
<span class="nostress">CISTER Research Unit</span><br>
<br>
<span class="highlight">ISEP - IPP</span> | Rua Dr. António Bernardino
de Almeida 431<br>
4200-072 Porto | Portugal <br>
T +351 22 83 40 529 | <a href="http://www.cister.isep.ipp.pt/people/stefan+m%2E+petters">Homepage</a>
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