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<p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#002060'>XScale is not a x86/IA32 architecture.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#002060'>On a system running OKL4 you cannot access any BIOS functions, because
they are all real mode implementations while OKL4 is running in protected mode.<o:p></o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#002060'><o:p> </o:p></span></p>
<p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#002060'>Frank<o:p></o:p></span></p>
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<p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif";
color:windowtext'>From:</span></b><span style='font-size:10.0pt;font-family:
"Tahoma","sans-serif";color:windowtext'> developer-bounces@okl4.org
[mailto:developer-bounces@okl4.org] <b>On Behalf Of </b>Stefan M. Petters<br>
<b>Sent:</b> Thursday, January 07, 2010 10:58 AM<br>
<b>To:</b> Frank Kaiser<br>
<b>Cc:</b> Peter Nguyen; developer<br>
<b>Subject:</b> Re: [okl4-developer] PMCs<o:p></o:p></span></p>
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<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Hi,<br>
<br>
Frank Kaiser wrote: <o:p></o:p></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#002060'>Hello</span><o:p></o:p></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#002060'> </span><o:p></o:p></p>
<p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#002060'>Most of modern x86 processors provide the TSC for performance
monitoring. According to what I remember from INTEL’s x86 architecture
documentation it is guaranteed that the TSC will not overflow within 10 years.
This is far beyond a system’s uninterrupted operating time, therefore I see no
reason for an overflow interrupt etc.</span><o:p></o:p></p>
<p class=MsoNormal><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#002060'>The common approach is to read and store the TSC at a tracepoint
and calculate time differences between associated tracepoints. The main
difficulty is to determine the absolute timebase, because this is highly
dependent on the specific CPU and chipset in use, and on the system’s clocking.</span><o:p></o:p></p>
<p class=MsoNormal>TSCs count CPU core clock cycles. So it becomes somewhat
iffy when you start frequency scaling. On some XScale processors you have the
option of saving power by gating the core clock. IIRC that means also the TSC
will be halted.<br>
Unless you do the energy saving thing, it becomes pretty trivial to find out
the core CPU frequency.<br>
Under Linux <br>
cat /proc/cpuinfo<br>
will tell you and BIOS usually also does.<br>
On Windows you can look up the System info.<br>
<br>
Regards,<br>
Stefan.<o:p></o:p></p>
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<p class=MsoNormal>-- <o:p></o:p></p>
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<p class=MsoNormal><span class=stress1><span style='font-size:9.0pt;font-family:
"Verdana","sans-serif"'>Stefan M. Petters</span></span><span style='font-size:
9.0pt;font-family:"Verdana","sans-serif"'><br>
</span><span class=nostress1><span style='font-size:9.0pt;font-family:"Verdana","sans-serif"'>CISTER
Research Unit</span></span><span style='font-size:9.0pt;font-family:"Verdana","sans-serif"'><br>
<span class=parstyle1> </span><br>
</span><span class=highlight1><span style='font-size:9.0pt;font-family:"Verdana","sans-serif"'>ISEP
- IPP</span></span><span class=parstyle1><span style='font-size:9.0pt'> | Rua
Dr. António Bernardino de Almeida 431</span></span><span style='font-size:9.0pt;
font-family:"Verdana","sans-serif"'><br>
<span class=parstyle1>4200-072 Porto | Portugal </span><br>
<span class=parstyle1>T +351 22 83 40 529 | <a
href="http://www.cister.isep.ipp.pt/people/stefan+m%2E+petters">Homepage</a> </span></span><o:p></o:p></p>
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