[okl4-developer] About L4 IPC for ARM architecture

[Joshua Root]

Yeonju wrote:
> Hi :)
> I have been studying OKL4(ver. 2.1). And I have a question about L4 IPC for
> ARM architecture. 
> 
> 
> In reference manual, there are five MRs(R3~R8) for IPC. Also I found this in
> "okl4_2.1\tools\magpie\test\fullsystem\pistachio\user\include\l4\armSyscall.h". 
> 
> Does L4 support only five MRs for IPC in ARM architecture? I mean...I woder
> how L4 deals with if one thread wants send messages more than 20 Bytes.

The message registers are virtual registers. There are 32 MRs, 6 of
which are backed by physical registers. The rest are backed by memory
locations in the UTCB.

If you want to transfer more data than will fit in the MRs, you use a
shared memory mapping or the MemoryCopy syscall.

- Josh