[okl4-developer] ARM versatile platform

[Nelson Tam]

Hi Lukas,

On 27/05/2008, at 8:06 PM, Lukas HANEL wrote:

> Digging further into the problem, I figured out, that the kernel loops
> in the instruction cache invalidation function.
> arch/arm/cpu/include/cache.h:
>    static inline void cache_invalidate_ilines(addr_t vaddr, word_t  
> size)
>
> I eventualy figured out, that the kernel increments a pointer by
> ICACHE_LINE_SIZE, which I did not set in my configuration and which  
> was
> hence zero.
>
> Naturaly I looked up the instruction cache attributes and set the
> correct values in my platform file. And fortunatly, now it works.
>
> This is odd with other platforms, which do not define instruction  
> cache
> attributes in their plat.cc
>
> So for arm926 cpu cores you also have to set the icache attributes in
> you plat.cc file.


You make a fair point.  Thanks for picking that up.

--
(nt)

Nelson Tam

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