[okl4-developer] clarifying L4-IPC

[Jorge Torres]

Hi okl4.org,

I want to explain to a friend of mine how L4 IPC works, and why is it
efficient,  since my understanding of it, is way empirical, It is probably
better to clarify with you guys first, so here it goes how I briefly
understand a general among L4 (blocking) IPC operations:

Lets say I have two threads Ta and Tb. where Ta is to send an IPC message to
Tb, prior to that Tb has to be on "waiting state", the state value is stored
by the u-kernel on thread's corresponding virtual registers at its
corresponding address space user thread control block (UTCB). Having done
so, Ta loads the message in its TCB message registers, and it performs the
"send"  syscall, microkernel checks if sender has permission to communicate
with the recipient, if true, The virtual registers real-addresses are mapped
into Tb's message virtual register's virtual addresses, (is the senders TID
stored on the recipient's TCB? or where?), Tb state is changed, and is sent
to the first place on the scheduling queue. It is very fast because: message
is never copied (since its based on mapping the same message onto the
respective virtual addresses) and since operation is granular, a TLB miss
wont happen.

Well that's somehow what I get, so please tell me how far is it from being
the truth.

Cheers,

Jorge
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