[okl4-developer] About the memory management in OKL4

[kashin Lin]

Hi,

thanks for your answering and i still have some questions:

1. after reading the documents, it seems the memory attributes in Iguana are
corresponds to the cache policy in micrikernel.
    (ex: L4_DefaultMemory -> DEFAULTPOLICY, ..., L4_IOMemory ->
DEVICEPOLICY)
    but some cache policy are not clear to me: for L4_DefaultMemory and
L4_IOMemory, are they caching policies or not?
    (for ARM architecture (arm926))

2. the new created memory section can be configured the cacheability through
memory attributes. but in original system memory,
   what are the original memory region placed the OKL4(include microkernel,
Iguana, Iguana application...) code and data 's cacheability set?

3. if i use CacheControl system call in Iguana application, what should i
pass for the first parameter(L4_SpaceId_t space)?

4. when i issue the following code:
   result = hardware_back_memsection(mem_sect, phys, L4_IOMemory);
   i found the implementation code "iguana_hardware_back_memsection_impl" in
iguana/server/src/iguana_server.c just set the L4_IOMemory into ms->
attribute
   without passing deep into pt_insert(). how could the mapcontrol system
know the memory attribute to be set?



best,
kashin

2008/6/13, Geoffrey Lee <glee at ok-labs.com>:
>
> On Fri, Jun 13, 2008 at 12:56:26AM +0800, kashin Lin wrote:
> > Hi,
> >
> > sorry, there is one more question:
> >
> > in OKL4 microkernel, there are some cache operations api. how to use
> these
> > api in an Iguana application?
> > for example, if a memsection X is set to cacheable and i want to
> Invalidate
> > the corresponding cache entry,
> > how to use those api to achieve it? (it seems it doesn't suit to pass
> Iguana
> > memsection as the parameters)
>
>
>
> If you just want to perform cache-based operations you may make use
> of the CacheControl() system call.
>
>
> >
> > best,
> > kashin lin
>
>
>         -gl
>
>
> >
> > 2008/6/13, kashin Lin <kashin08 at gmail.com>:
> > >
> > > Hi,
> > >
> > > i want to understand the memory management in OKL4 and has following
> > > questions:
> > >
> > > 1. for using virtual memory in a supported architecture (ex: arm926),
> it
> > > need to setup the "translation table" for
> > >     the hardware MMU (TLB) in system initial time to indicate the virt
> &
> > > phys mapping and sets the memory region
> > >     are cacheable or not.
> > >     i wonder how does OKL4 set the "translation table"?
> > >     ie. what address ranges are included, how the default virt to phys
> > > maps? (direct mapping?), cacheability?
> > >
> > > 2. i got confused about the address space in OKL4 microkernel and
> memory
> > > section in Iguana. it seems they are
> > >     all mappings from virt to phys. what is the relationship between
> them?
> > >     do they use other data structures to maintain the mapping or effect
> the
> > > "translation table" directly?
> > >
> > > 3. in following codes:
> > >     mem_sect = memsection_create_user(leng, &virt);
> > >     result = hardware_back_memsection(mem_sect, phys, L4_IOMemory);
> > >     will the memory section (base is "virt") cacheable? (cacheability
> is
> > > controled by attribute L4_IOMemory or function hardware_back_memsection
> ?)
> > >
> > > 4. if i using above codes in two Iguana application (create two
> memsections
> > > in two application to map to the same phys),
> > >     will they get the same "virt"?
> > >
> > >
> > > thanks in advance.
> > >
> > >
> > > best,
> > > kashin lin
> > >
> > >
>
>
> > _______________________________________________
> > Developer mailing list
> > Developer at okl4.org
> > https://lists.okl4.org/mailman/listinfo/developer
>
>
> --
>
>
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