[okl4-developer] About the memory management in OKL4

[kashin Lin]

Hi,

sorry, there is one more question:

in OKL4 microkernel, there are some cache operations api. how to use these
api in an Iguana application?
for example, if a memsection X is set to cacheable and i want to Invalidate
the corresponding cache entry,
how to use those api to achieve it? (it seems it doesn't suit to pass Iguana
memsection as the parameters)

best,
kashin lin

2008/6/13, kashin Lin <kashin08 at gmail.com>:
>
> Hi,
>
> i want to understand the memory management in OKL4 and has following
> questions:
>
> 1. for using virtual memory in a supported architecture (ex: arm926), it
> need to setup the "translation table" for
>     the hardware MMU (TLB) in system initial time to indicate the virt &
> phys mapping and sets the memory region
>     are cacheable or not.
>     i wonder how does OKL4 set the "translation table"?
>     ie. what address ranges are included, how the default virt to phys
> maps? (direct mapping?), cacheability?
>
> 2. i got confused about the address space in OKL4 microkernel and memory
> section in Iguana. it seems they are
>     all mappings from virt to phys. what is the relationship between them?
>     do they use other data structures to maintain the mapping or effect the
> "translation table" directly?
>
> 3. in following codes:
>     mem_sect = memsection_create_user(leng, &virt);
>     result = hardware_back_memsection(mem_sect, phys, L4_IOMemory);
>     will the memory section (base is "virt") cacheable? (cacheability is
> controled by attribute L4_IOMemory or function hardware_back_memsection ?)
>
> 4. if i using above codes in two Iguana application (create two memsections
> in two application to map to the same phys),
>     will they get the same "virt"?
>
>
> thanks in advance.
>
>
> best,
> kashin lin
>
>
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