[Developer] AVR32 port?

[Gernot Heiser]

>>>>> On Mon, 23 Apr 2007 10:17:29 -0500, Michael LeMay <mdlemay2 at cs.uiuc.edu> said:
ML> Hello,
ML> I have read numerous papers on L4, and have noted that hardware-walked 
ML> page tables have been the source of some difficulties throughout L4's 
ML> past,

There aren't any difficulties with hardware-walked page tables, to the
contrary, hardware walkers tend to be faster than software
walkers. What is an issue for any system with high context-switching
rates (as a microkernel-based system) is untagged TLBs, as they
increase the indirect context-switching costs.

ML> although L4 certainly has the most clever techniques for solving 
ML> such problems.  Recently, Atmel released the AVR32 architecture with 
ML> software page tables, a Harvard architecture, and even lower typical 
ML> power consumption than ARM cores.  This seems like an interesting 
ML> architecture to target with L4.  I'm curious, do you have any plans for 
ML> looking at it in the future?  Thank you!

Our general approach is that we support architectures the market
wants. For obvious reasons we don't want to say more at this time...

Gernot